arete_arix A3000 slotfn Feb88 free download

File name A3000_slotfn_Feb88.pdf

Feb 10 11:01 1988 slotfn.h Page 1 This describes the appearance of the processor module as seen by other modules on the CSS bus. Read status Register: An automatic register may be read (byte or long) at physical address offset:Oxfffffffc. The register is "automatic" because it responds without assistance from the processor. 31-------------24 23---------21 20 19 18--16 15-------8 7-------------0 +----------------+--------------+----+----+------+----------+-----------------+ I I I cmd I (board id) I I unpredictable lipl2 ipl1 iplO halt pend 1 1 1 I mail reg I 0 0 0 0 0 0 1 0 I +----------------+--------------+----+----+------+----------+-----------------+ ipl2,1,0 reflect the (low true) value at the processor input halt=O indicates the processor has a double bus error cmd-pend=l indicates the command buffer is full mail reg is loaded by the processor at BUS MAIL BYTE. Command register: Commands to read or write are accepted at offset:Ox??????OO (where? represents 4 don't care bits), as required by the CS8 Bus Specification. The register captures four bytes of address and four bytes of data. The data captured from a read command is not predictable. Receiving a command, except the automatic read, causes a Non-Maskable Interrupt to be asserted at the processor, and the cmd-pend bit to be set. The processor's firmware is expected to respond to the command. Further commands cannot be received until the processor increments its ready-count on the arbiter. HARDWARE LIMITATIONS: Since the equipment for sending DATA RESPONSEs is not usable while the processor is executing from main memory or testing cache or mmu, read commands are not recommended as part of the normal protocol. Also, the type value is not captured, so the module has no easy way to tell an arriving read from a write command. I.t- '1\ l--\ r . \. Feb 10 11:01 1988 slotfn.h Page 2 l 1_._".,,_...